Conventional integrated circuit design involves several complex steps. For example, a circuit designer may use software tools to define the operation of each functional element of an integrated circuit at each clock cycle. Such a definition is known as a Register Transfer Level (RTL) specification. A logic synthesis operation may then be applied to the RTL specification to generate a list of logic gates and interconnections between the logic gates. The list may be referred to as a netlist, and may be used to implement the RTL specification.
A modern netlist may comprise millions of logic gates and associated interconnections. Conventional design tools may parse the netlist and determine placement of the logic gates and routing of the interconnections on an integrated circuit based thereon. The placement and routing information may be used to generate photolithography masks, which in turn may be used to fabricate the integrated circuit. The photolithography masks may consist of gate masks used to fabricate the logic gates of the netlist and routing masks used to fabricate the interconnections therebetween.
It may be desirable to change an original netlist so that it is functionally equivalent to a new specification. For example, a designer may wish to change a functional aspect of an original netlist due to an Engineering Change Order and/or due to an error in the original netlist. The designer may therefore create a new RTL specification and synthesize the new netlist therefrom. Alternatively, the designer may directly edit the original netlist to create a new netlist. The latter alternative may be employed late in the design process, because doing so will reserve most of the engineering effort invested in the original netlist.
The specific changes required to the new netlist are dependent upon the logical difference between the original netlist and the new netlist. Since a logical difference between two logic functions may typically be expressed in many different forms, the details of the change may differ based on the form in which the logical difference is expressed.
FIG. 1 is a logical diagram of original netlist G1 and “target” netlist G2. The present example will illustrate changes to netlist G1 that result in functional equivalence with target netlist G2. Either of “single-fix” signals S1 and S2 may be changed to accomplish this goal. FIG. 2A illustrates netlist G1 after changing signal S1. Specifically, signal S1 has changed from (c^d)′ to (c^d)′+e′. The function (c^d)′+e′ may be called a rectification function because it rectifies a functional difference between original netlist G1 and target netlist G2. FIG. 2B illustrates a change of signal S2 from (ab)′ to rectification function (ab)′e. Both systems shown in FIG. 2A and FIG. 2B are functionally equivalent to netlist G2 of FIG. 1.
Systems have been proposed and for locating single-fix signals and deriving corresponding rectification functions. Such systems are typically not scalable, limited to simple correcting-models (e.g. gate type change, connection change, etc), and/or otherwise inefficient. Accordingly, further systems are desired for efficiently determining a change to an original netlist that will result in functional equivalence between the changed netlist and a target netlist exhibiting desired functionality.
Typically, a changed netlist will include some gates that were not present in the original netlist, will lack some gates that were present in the original netlist, and will reflect some different interconnections between the included gates. Accordingly, in order to fabricate an integrated circuit based on the changed netlist, new gate masks must be generated at a significant cost. Systems are therefore desired to implement a changed netlist using gate masks of an original netlist.